From: Varun Wadekar <vwadekar@nvidia.com>
Date: Thu, 3 Jan 2019 01:53:15 +0000 (-0800)
Subject: Tegra210: Enable WDT_CPU interrupt for FIQ Debugger
X-Git-Url: http://git.openwrt.org/%22https:/collectd.org//%22/%22https:/collectd.org/%22?a=commitdiff_plain;h=51a5e593d654f46c7ab367eaa135923e25c0ad62;p=project%2Fbcm63xx%2Fatf.git

Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.

Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
---

diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index 0285867a..6a820f00 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -43,6 +43,11 @@
 #define TEGRA_GICD_BASE			U(0x50041000)
 #define TEGRA_GICC_BASE			U(0x50042000)
 
+/*******************************************************************************
+ * Secure IRQ definitions
+ ******************************************************************************/
+#define TEGRA210_WDT_CPU_LEGACY_FIQ		U(28)
+
 /*******************************************************************************
  * Tegra Memory Select Switch Controller constants
  ******************************************************************************/
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index 6246dde9..25105ba1 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -1,15 +1,22 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <arch_helpers.h>
-#include <bpmp.h>
 #include <cortex_a57.h>
 #include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/interrupt_props.h>
 #include <drivers/console.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv2.h>
+#include <bl31/interrupt_mgmt.h>
+
+#include <bpmp.h>
+#include <flowctrl.h>
 #include <platform.h>
 #include <security_engine.h>
 #include <tegra_def.h>
@@ -137,10 +144,25 @@ void plat_early_platform_setup(void)
 	}
 }
 
+/* Secure IRQs for Tegra186 */
+static const interrupt_prop_t tegra210_interrupt_props[] = {
+	INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY,
+			GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+};
+
 /*******************************************************************************
  * Initialize the GIC and SGIs
  ******************************************************************************/
 void plat_gic_setup(void)
 {
-	tegra_gic_setup(NULL, 0);
+	tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props));
+
+	/* Enable handling for FIQs */
+	tegra_fiq_handler_setup();
+
+	/*
+	 * Enable routing watchdog FIQs from the flow controller to
+	 * the GICD.
+	 */
+	tegra_fc_enable_fiq_to_ccplex_routing();
 }